The present invention generally relates to a transistor and more particularly, to a thin film transistor (normally abbreviated as TFT) having a construction which is intended to achieve an improvement on yield in the manufacture thereof.
Recently, in the field of a liquid crystal active matrix display, vigorous studies have been made into an active matrix substrate in which thin film transistors are created in the form of a matrix on an insulative substrate. Available semi-conductor materials for this purpose include polySi, a-Si, Te, CdSe, etc.
In FIG. 5, and FIG. 4 showing a cross section taken along the line IV--IV of FIG. 5, one example of the construction of a conventional thin film transistor TFT employing a-Si is illustrated, in which a gate wiring 3 for connecting gate electrodes 2 if formed on a glass substrate 1 by a metallic material such as Ta, Mo, Ti Al or the like in a film having a thickness of 200 to 3000 .ANG.. The gate wiring 3 is provided with a branched portion 3a and the thin film transistor TFT is formed on said branched portion 3a as a center. Over the gate electrode 2, a gate insulating film 4 (not shown in FIG. 5) of silicon nitride (referred to as SiNx hereinafter) in the thickness of 1000 to 2000 .ANG. is formed by a plasma CVD (chemical vapor deposition) process. Further formed on the gate insulating film 4 is an a-Si layer 5 having a thickness of 1000 to 3000 .ANG. by the plasma CVD process. A source wiring 7 for connecting source electrodes 6 is formed to intersect at right angles with the gate wiring 3. The source electrode 6 and a drain electrode 8 are both formed by a metallic material such as Ta, Mo, Ti, Al or the like in the thickness of 2000 to 10000 .ANG.. In connection with the above, it is preferable to dispose another a-Si film 9 having a thickness of 500 to 2000 .ANG. and doped with phosphorus, between the source electrode 6 and drain electrode 8 and the a-Si film 5 so as to achieve ohmic contact therebetween. In the manner as described above, the thin film transistors, TFT, are formed in the shape of an array at respective intersections between the gate wiring 3 and the source wiring 7. Although not particularly shown, picture element electrodes corresponding to the respective thin film transistors TFT are formed to contact the drain electrodes 8.
In an active matrix substrate employing the thin film transistors, the respective intersections are driven by a linear sequential system. More specifically, scanning signals are applied from one gate wiring to be scanned, while data signals are inputted from each source wiring. There are a large number of intersections between the gate wirings and source wirings, for example, at 62,500 spots in a 250.times.250 matrix. If leakage should take place between the gate and source, even at one of these numerous intersections, a line fault in the form of a cross is inevitably produced at the equivalent gate wiring and source wiring, thus making the display unsuitable for actual application, with the yield of the active matrix substrate being reduced to zero. Accordingly, as the number of the gate wirings and source wirings increases, positive insulation between the gate and source is even more necessary.
As in the thin film transistor shown in FIGS. 4 and 5, in the case where the gate insulating film is formed by only one layer of the thin film 4, it is extremely difficult to reduce to zero, the leakage between the gate and source which takes place due to presence of foreign matter, pin holes, etc. As countermeasures against the above disadvantage, there has been proposed a practice in which a double-layered film of an anodized film of gate metal and SiNx film by the plasma CVD is employed, A film of tantalum pentoxide obtained by anodizing tantalum is very stable both chemically and physically, and characterized in that is has a dielectric constant larger than that of a silicon group material. Moreover, since the anodized film is produced by a reaction in a solution, there is such an advantage that, even in the case where pin holes, cracks, foreign matter, etc. are present in the gate metal, such portions are anodized to be covered by an insulating material.
FIG. 6 shows one example of a thin film transistor TFT in which tantalum is employed for the gate metal, while a double-layered film of tantalum pentoxide formed by anodizing and SiNx film formed by the plasma CVD is adopted as the gate insulating film. The thin film transistor of FIG. 6 includes an insulative substrate 1, and a gate electrode 11 of tantalum, an anodized tantalum film 12, an SiNx film 13 formed by the plasma CVD, a semi-conductor layer 14, a source wiring 15 and a drain electrode 16 which are all sequentially laminated on said insulative substrate 1 in the above order. In the thin film transistor in FIG. 6, although the leakage between the gate and source has been reduced to a large extent as compared with that in the thin film transistor having the construction as shown in FIG. 4, the yield thereof in manufacture is not as yet favorable.
As a result of the investigation into the cause of the above disadvantage through "copper decoration method", it has been discovered that the leakage between the gate and source frequently takes place at portions where edges of the gate and the source intersect each other (i.e., at hatched portions in FIG. 5), and that in a portion where a semi-conductor film is present between a gate electrode and source electrode, the degree of leakage occurrence is by far smaller than that at a portion where no semi-conductor film is present therebetween. The above phenomenon is considered to be attributable to the fact that, as shown in FIG. 7, since the anodized film 12 of the gate electrode 11 by tantalum grows isotropically, edges of the gate electrode 11 have a considerably sharp angle, and the SiNx film 13 laminated thereover becomes very thin at such edge portions, with a consequent reduction in the withstand voltage as a gate insulating film. The phenomenon may also be ascribed to the fact that the nature of the gate insulating film is different between a flat portion and a stepped portion, and the stepped portion is inferior to the flat portion in the aspect of insulation.